31 Aug '17, 10pm

Hybrid PWM/R2R #DAC improves on both:

Hybrid PWM/R2R #DAC improves on both:

To compare with the traditional simple low-pass filter (Figure 2 ) you should remember that the output resistance of an R-2R ladder is R, and since I propose paralleling two resistors from the array to form R (with individual resistors for 2R), a 10kΩ array yields 5kΩ output resistance. That is what I used for the traditional approach along with the same 1µF capacitor. I set the PWM to 50% duty cycle as that is where the worst ripple occurs. The results of the simulation (Figure 3 ) show the traditional approach with about 4mV of ripple, while the first option (adding the three new bits to the original eight) resulted in 493µV of ripple, just about one eighth. The second option (increasing the PWM clock by eight, leaving eight bits total) generated only 61µV, around one sixty-fifth of the original.

Full article: http://www.edn.com/design/analog/4458772/Hybrid-PWM-R2R-D...

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