18 Nov '17, 3am

Hardware Emulation: A Weapon of Mass Verification

Dr. Lauro Rizzatti, Verification Consultant Despite the third adjustment to Moore’s Law, which now sets the doubling of transistors in an integrated circuit to about two years, the march continues on toward larger and larger designs/devices. The average design size today hits or exceeds 50 million application-specific integrated-circuit (ASIC) gates, with individual blocks topping out at over 10 million gates. Top-end designs in leading semiconductor companies routinely surpass 100 million gates. The largest designs in the processor/graphics business have already reached one billion gates, or will surpass that number in the near future. Driving this steep rise in design complexity is demand for new features and capabilities either added to existing products or implemented in completely new designs. As if the soaring silicon complexity isn’t enough, the swell of embedded so...

Full article: http://www.electronicdesign.com/test-measurement/hardware...

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