13 Feb '18, 4pm

Mark your calendar! Talk to our experts at #DVCon on Monday Feb 26. Get the agenda here:

DVCon is the premier conference for functional design and verification, bringing you information from the leading edge of technology, techniques, standards, and methods. Visit Cadence in booth 702 and we’ll introduce you to the latest tools, methodologies, and support you need for designing and verifying complex silicon, SoCs, and systems. Talk to our experts focused on VIP and IC/SoC/system design and verification. Join us for these presentations, posters, panels, and tutorials on: Monday, February 26: 9:00am - 12:00pm | Oak/Fir Portable Test and Stimulus: The Next Level of Verification Productivity Is Here 2:00pm - 5:00pm | Oak/Fir IEEE-Compatible UVM Reference Implementation and Verification Components Thursday, March 1: 8:30am - 12:00pm | Donner SoC Verification Speed – More is Better 12:15pm - 1:45pm | Donner Smarter and Faster Verification: Beyond Brute Force 2:00pm ...

Full article: https://www.cadence.com/content/cadence-www/global/en_US/...

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