08 Mar '13, 7pm

Pumping 1080p video out of an FPGA

I recently completed a PCIe soft IP core design; the connection between the core and the PHY was 250MHz (4ns). You’re required to use time constraints (and give it an idea of how long each trace is between the FPGA and PHY) to get it to work. That was using a device without built-in PHYs; the same device (Altera Cyclone IV) comes in a variant that has hardware transcievers capable of 5Gbps, and the newer devices can go much faster yet. Constraining your design is essential to getting these things to work. It’s generally frowned upon to manually place anything because as clock rates climb and circuit complexity increases it’s almost impossible to know better than the fitter about what should go where. You instead say “these signals have these constraints” and let the fitter do the work. It’s not only possible to achieve these data rates without manually placing — it is actu...

Full article: http://hackaday.com/2013/03/08/pumping-1080p-video-out-of...

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