29 Apr '13, 1pm

Chip design is crucial to Europe, says Cadence v-p

Alexander Duesener, v-p of worldwide field operations in EMEA for Cadence Design Systems believes chip designers have a crucial role in maintaining Europe’s strengths in wireless and automotive systems. The biggest challenge in complex SoC design is verification. How are designers in Europe tackling complex chip verification? Alexander Duesener: As process nodes shrink and SoC complexity grows, IC verification becomes more and more challenging. Studies have shown that verification and debugging can consume most of the IC design cycle. Breaking through this bottleneck, while at the same time ensuring product quality and reliability, is crucial to success in European strongholds such as wireless and automotive. Fortunately, there are various standardised methodologies that can help. For example, more and more design teams in Europe are adopting metric-driven verification, wh...

Full article: http://www.electronicsweekly.com/articles/29/04/2013/5601...

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