30 Nov '13, 8pm

Learn how to *Optimize Your PCB Decoupling Capacitors & Remain a Person of Integrity* - #PCB Design Blog

How much integrity is too much? If your PCB designs apply one or more decoupling capacitors (decaps) per power pin, then you may have too much integrity - power integrity, that is. Your designs are also more expensive than necessary and your decap mounting structures have vias in areas that could be better applied for signal routing. If you reduce the number of decaps, will you have less integrity? Will your PCB's Power Delivery Network (PDN) performance (and your performance as a designer) be challenged? Successful selection of the type and quantity of decaps and their placement locations depend on many factors. Included in the factors are: device switching current, target impedance profiles, capacitance and inductance (ESL) of the decaps, mounting inductance of each decap and device, and PDN inductance between device and decap. Even with the availability of detailed simu...

Full article: http://www.cadence.com/Community/blogs/pcb/archive/2013/1...

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