28 Nov '11, 10am

New LatticeECP4 Family Redefines Low Cost, Low Power FPGAs, Features High Performance Innovations: New LatticeEC...

High Quality SERDES and Hardened Communication Engines The LatticeECP4 FPGAs contain up to 16 CEI-compliant 6 Gbps SERDES channels with embedded Physical Coding Sub-layer (PCS) blocks in both low cost wire-bonded and high performance flip chip packages, giving customers the option to deploy the LatticeECP4 FPGA in chip to chip as well as long haul backplane applications. The versatile and configurable SERDES/PCS can be seamlessly integrated with the hardened Communication Engines to economically build complete high bandwidth sub-systems. The Communication Engines offer up to 10X the power and cost reduction of similar implementations in FPGA fabrics. The LatticeECP4 Communication Engines portfolio includes solutions for PCI Express 2.1, multiple 10 Gigabit Ethernet MAC and Tri-speed Ethernet MACs as well as Serial Rapid I/O (SRIO) 2.1. The combination of SERDES/PCS and Com...

Full article: http://www.design-reuse.com/news/27895/6g-serdes-latticee...

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Lattice targets performance wireless designs wi...

electronicsweekly.com 28 Nov '11, 7am

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design-reuse.com 28 Nov '11, 11am

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singaporesales.sg 28 Nov '11, 1am

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earth911.com 28 Nov '11, 3pm

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environmentalhealthnews.org 28 Nov '11, 11am

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It’s interesting to see what Google thought it could contribute to the field of solar thermal power plant engineering. The...

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renewableenergyworld.com 25 Nov '11, 6pm

It’s interesting to see what Google thought it could contribute to the field of solar thermal power plant engineering. The...

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getsolar.com 21 Nov '11, 10pm

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jetsongreen.com 27 Nov '11, 5am

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Warning: High Frequency

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In laboratory tests, several commercially available Industrial Ethernet devices were tested with a 2 ms cycle time under v...

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IBM's Blue Gene/Q; petaflops on low power

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eetimes.com 17 Nov '11, 9pm

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