29 Dec '13, 7am

Do you know "What Comes Next in IC Fault Modeling?" Find out in @RichardGoering's blog:

The way in which IC designers model potential faults has a direct impact on the quality of silicon and the cost of test. At advanced nodes, fault models must evolve to more accurately represent real silicon effects - without significantly increasing time on the tester. This conflicting set of demands is one of the key challenges facing design for test (DFT) methodologies today. I wrote some articles about DFT in the 1980s and 1990s, and fault models were fairly simple back then. Designers were representing silicon defects with stuck-at-0 and stuck-at-1 fault models. The idea was that internal nodes could literally be "stuck" at one of these values due to a manufacturing error. A recent conversation with Mike Vachon, engineering group director for Encounter Test at Cadence, brought me up to date. He noted that the "stuck-at" fault models were typically all that was needed u...

Full article: http://www.cadence.com/Community/blogs/ii/archive/2013/12...

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