30 Jan '14, 12am

Designing Flip-Flops with Python and Migen

Actually, you are missing the point. Migen should be thought of as ‘generate’ on steroids, with a DSL of the synthesizable subset of Verilog. Migen really doesn’t restrict you in terms of synthesizable code. Sure, you can’t emit delays, but you can’t synthesize those either. You can directly instantiate FPGA primitives (LUTs) if you really want. For clocking – you’d just directly instantiate a DCM + whatever BUFGs/CLK muxes/etc that you need. With regard to optimization – I’ve done plenty of manual floorplanning before, and even written Verilog to the level of directly instantiating + LOCing LUTs for the critical path (ISE wouldn’t come up with the fastest design on its own). I can do a lot of the same with Migen; except I have the whole of python to automate things for me (I want a bunch of SLICEs LOCed in a column so I can do something weird with the carry chains? no pro...

Full article: http://hackaday.com/2014/01/29/designing-flip-flops-with-...

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