23 Jan '12, 4pm

Location Is Everything: Improving Performance with Interactive LDE Estimation: via @ee_times #EDA #SemiEDA

Location Is Everything: Improving Performance with Interactive LDE Estimation: via @ee_times #EDA #SemiEDA

Over the past 40 years, the semiconductor industry has continued its rapid pace offering more compact electronic products with higher speed and increasing functionality at lower cost. This rapid growth has been fueled by the industry’s ability to scale MOS transistors as predicted by Moore’s law. Yet, when technology nodes have reached the sub 90nm threshold, performance improvement anticipated from scaling failed to match expectations within the analog design community. This is largely due to the emergence of Well Proximity Effects (WPE) and Shallow Trench Isolation (STI) stress effects that were not accounted for in previous process nodes. WPE and STI related stresses have been proven to severely disrupt the electrical characteristics of MOS devices. Such effects depend on device placement during the layout design phase, hence the more generic description: layout-depende...

Full article: http://www.eetimes.com/design/eda-design/4235047/Location...

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