29 Feb '12, 7pm

#DVCon user panelists: Is low power design worth the costs? Report at #CDNS #EDA #semiEDA

#DVCon user panelists: Is low power design worth the costs? Report at #CDNS #EDA #semiEDA

Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference Feb. 28, three engineering managers and two EDA vendor representatives painted this broader picture - and came up with a lot of great advice for anyone considering low-power design.

Full article: http://www.cadence.com/Community/blogs/ii/archive/2012/02...

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