02 Mar '12, 2pm

MathWorks’ MATLAB now supports HDL code generation #EDA #FPGA #ASIC #SOC

MathWorks’ MATLAB now supports HDL code generation #EDA #FPGA #ASIC #SOC

There are a variety of trends that are driving the rise of FPGAs in the marketplace. These include the rise of complex applications, the adoption of application processors, and increasing design complexity and associated gate counts. While designing to meet these requirements, engineers are being tasked with compressing design timeframes, managing project costs and adopting automatic verification for FPGA hardware-in-the-loop. Over the years, an increasing number of engineers have grown to rely on MathWorks to address these seemingly disparate challenges through a complete environment for modeling, analysis, HDL code generation, and verification. Previous releases of the tools included support for automatic C code generation. Now MathWorks have added HDL code generation (VHDL and Verilog). The latest tool suite from MathWorks allows engineers to work in their preferred des...

Full article: http://www.eetimes.com/electronics-products/electronic-pr...

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