D&R Industry Articles: SoC (System on Chip), Silicon IP, Semiconductor IP, Software IP, Verification IP, Core, Design Reuse

Embedded 3D graphics is here, but 2D is still important: Here's why: Embedded 3D graphics is here, but 2D is sti...

Unified C-programmable ASIP architecture for multi-standard Viterbi, Turbo and LDPC decoding This paper describes an ASIP decoder template suitable for multi-standard Viterbi, Turbo and LDPC decoding. We show architecture fitness for WLAN, WiMAX and 3GPPLTE standards, although various other standards can also be mapped, since the architecture is capable of supporting any interleaver pattern and programmable in C. The ASIP core consists out of a SIMD with multiple slots each with their dedicated functionality. Because of their block based approach and possible parallelization decoding strategy, both Turbo and LDPC were mapped using the same concept. Support for Viterbi decoding is made possible through a dedicated decoding pipeline with radix-4 to boost performance well above the tough throughput and latency requirements of the 802.11n standard.

Full article: http://www.design-reuse.com/articles/