17 Apr '12, 7am

Posted Today: #FPGA Design Guide Pt4 - SPI Interface | on @element14

Posted Today: #FPGA Design Guide Pt4 - SPI Interface | on @element14

Well we can start by just looking at the counter. When the counter has a value of 0 or 1 we can set the CS line high. At count 2 we can drive the CS line low knowing that on the next clock we will get our first bit out. So thats count value 3 to 34 that will have valid data in them. These can be placed into a buffer that is shifted one bit every time too. hence data in collected one bit at a time. Once we get to count 34 we can ‘register’ the buffer into our 32 bit output. Registering it means its gets locked in so the buffer can be used again without effecting the output. It's actually nothing more that a big 32 bit latch. Also on count 34 and also during count 35 we will drive the CS line high and because our counter resets itself back to 0 when it sees 35, the whole thing starts all over again with no outside help. This is useful as we want a continuous flow of data fro...

Full article: http://www.element14.com/community/groups/fpga-group/blog...

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