New IDE from @xilinxinc - FPGA Design Suite Generates Global Minimum Layout via @ElectronicDesgn

FPGA Design Suite Generates Global Minimum Layout

New IDE from @xilinxinc - FPGA Design Suite Generates Global Minimum Layout via @ElectronicDesgn

Users of Xilinx’s Series 7 FPGAs will have a choice between two development tools. Now in its 13th revision, Xilinx’s ISE supports all of the company’s FPGAs. The Vivado Design Suite supports all of the Series 7 FPGAs and will be the development tool for all future FPGAs from Xilinx. The company does have an upward migration path, with Vivado able to load ISE projects. Existing projects are likely to remain on ISE, but new projects may take advantage of Vivado and its improved capabilities. Figure 1. Layout on the 1.2M logic cell Virtex-7 2000T FPGA can be challenging. The left side was completed using ISE, requiring 13 hours and 16 Gbytes of memory, while the right side was finished using Vivado running for only five hours and using only 9 Gbytes. Xilinx’s multi-slice 1.2M logic cell Virtex-7 2000T FPGA (see “10,000 Connections Between FPGA Slices” at electronicdesign.com...

Full article: http://electronicdesign.com/article/digital/fpga-design-s...

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@DIYEngineering » 26 Apr '12, 10pm
FPGA Design Suite Generates Global Minimum Layout - By William WongUsers of Xilinx’s Series 7 FPGAs will have a choi... [link]
@BruceFienberg » 26 Apr '12, 8pm
RT @AltEmbedded: New IDE from @xilinxinc - FPGA Design Suite Generates Global Minimum Layout [link] via @ElectronicDesgn
@AltEmbedded » 26 Apr '12, 8pm
New IDE from @xilinxinc - FPGA Design Suite Generates Global Minimum Layout [link] via @ElectronicDesgn
@pauldubos » 02 May '12, 6pm
FPGA Design Suite Generates Global Minimum Layout [link] via @ElectronicDesgn