07 Jan '15, 5pm

High-Level Synthesis Uncovers PPA Tradeoffs of Various Hardware Accelerators @Cadence

High-Level Synthesis Uncovers PPA Tradeoffs of Various Hardware Accelerators @Cadence

For a configurable architecture, we reused the model of the fixed-function hardware just described. An ARM AMBA AXI4 bus slave interface was added to the SystemC model. The AXI4 model, a synthesizable SystemC model developed by Cadence and CircuitSutra , has both TLM- and PIN-level interfaces to support very fast design verification and synthesis. The host processor uses the ARM AMBA AXI4 interface to program the coefficients of the FIR filter. This results in a larger circuit and slightly more power consumption than the fixed-function implementation, but with added flexibility. This configurable accelerator could be applied to a number of different application domains.

Full article: http://electronicdesign.com/eda/high-level-synthesis-unco...

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