27 Feb '15, 10pm

EE Times Transactors -- Expanding the Role of FPGA-Based Prototypes FPGA-based prototypes offer unbeatable flexibi…

EE Times Transactors -- Expanding the Role of FPGA-Based Prototypes FPGA-based prototypes offer unbeatable flexibi…

Block-level prototyping: Mapping an entire design to an FPGA prototype can be challenging, especially when a large number of devices is needed. The use of transactors allows mapping designs block-by-block and verifying each block against its RTL-based simulation. This can be a very effective methodology, especially when separate teams are developing IP blocks independently. This approach can prevent issues from surfacing during integration. Simulation acceleration: RTL-level simulation alone can be prohibitively slow for verifying large designs. Mapping designs from a simulation environment to an FPGA prototype provides a high-performance, cycle-accurate test environment. Systems like this can run in the hundreds of KHz, typically out-pacing RTL-level simulation by three orders of magnitude. Design debugging: Debugging a complex design in an FPGA can be difficult, especial...

Full article: http://www.eetimes.com/author.asp?section_id=36&doc_id=13...

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