31 May '12, 7pm

Cadence Announces STMicroelectronics has Taped Out 20-Nanometer Test Chip Using Cadence Tools #CDNS #EDA

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that it has contributed to STMicroelectronics having taped out a 20-nanometer test chip, incorporating custom analog and digital methodologies to enable mixed-signal SoC design at this advanced process node. Engineers from the two companies collaborated closely to develop technologies and deploy methodologies using the Cadence Encounter and Virtuoso platforms to enable design, implementation and signoff, in addition to development of foundational IP and a SKILL-based process design kit (PDK) for the 20-nanometer process. This 20-nanometer tapeout marks an industry milestone for Cadence as the leader in delivering an end-to-end mixed-signal design flow for 20 nanometers. As part of this collaboration, STMicroelectronics has deployed the full Cadence® 20-nanometer fl...

Full article: http://www.cadence.com/cadence/newsroom/press_releases/Pa...

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