29 May '15, 11am

An Open Source Toolchain For iCE40 FPGAs

An Open Source Toolchain For iCE40 FPGAs

FPGAs are great, but open source they are not. All the players in FPGA land have their own proprietary tools for creating bitstream files, and synthesizing the HDL of your choice for any FPGA usually means agreeing to terms and conditions that nobody reads. After months of work, and based on the previous work of [Clifford Wolf] and [Mathias Lasser], there is a fully open source Verilog to bitstream development tool chain for the Lattice iCE40LP , with support for more devices in the works. Last March, we saw the reverse engineering of the Lattice ICE40 bitstream , but this is a far cry from a robust, mature development platform. Along with Yosys , also written by [Clifford Wolf] it’s relatively simple to go from Verilog to an FPGA that runs your own code. Video demo below, and there’s a ton of documentation over on the Project IceStorm project page . You can pick up the re...

Full article: http://hackaday.com/2015/05/29/an-open-source-toolchain-f...

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