29 May '15, 7pm

Extraction Challenges Grow in Advanced Nanometer IC Design

Extraction Challenges Grow in Advanced Nanometer IC Design

Successive generations of foundry process technologies enable ever-increasing design density, performance, and power savings, if only designers can deal with growing challenges. Innovative new process features such as FinFET transistors require a significant increase in the accuracy of parasitic extraction — the creation of an accurate analog — for simulation and analysis to verify performance of the physical design. Here are some of the new extraction challenges and how tool technology has evolved to meet the new requirements. What drives new tool requirements Integrated circuit designers need to extract the detailed electrical properties of an IC after it has been committed to a specific physical layout so they can do static analysis and simulation to ensure the IC will function properly and meet critical performance requirements. Especially at 16nm and below, it is para...

Full article: http://www.eetimes.com/author.asp?section_id=36&doc_id=13...

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