09 Nov '12, 10pm

System Update - FPGA DSP, OpenCL; 14nm ARM core; Free dev tools | EDN #EDA #CDNS

Study examines implementing floating-point DSP on Altera FPGAs Altera announced results of a benchmark study performed by Berkeley Design Technology Inc. (BDTI) on implementing floating-point DSP designs on Altera 28 nm FPGAs. As much an examination of Altera’s DSP Builder Advanced Blockset design flow as FPGA performance, the study "...debunks the myth that FPGAs are limited to high-performance fixed-point processing," according to Alex Grbic, Altera product marketing director. For the study, BDTI looked at implementation of single-precision complex-data IEEE 754 floating-point Cholesky and QR solvers modeled in MathWorks Simulink using the Altera DSP Builder Advanced Blockset. The design flow combined the Altera DSP Builder Advanced Blockset, Altera’s Quartus II software tool chain and ModelSim simulator, and MathWorks MATLAB and Simulink tools. BDTI conducted the study ...

Full article: http://www.edn.com/electronics-blogs/systems-interface/44...

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