31 Dec '16, 3pm

Latch-Based RAMs and the Hidden Capacitor

Meaning, the self capacitance is able to supply sufficient current to maintain the data state if the device is momentarily taken outside its normal operating range and subjected to zero or reverse voltage. This means any successful write scheme must be able to take the selected device outside its operating window for sufficient time to fully discharge any self capacitance and to allow any long lifetime carriers to be absorbed. While at the same time ensuring any excursions below the holding current and voltage for unselected devices in the conducting state are of a short enough duration to allow the device to recover to that state.

Full article: http://www.eetimes.com/author.asp?section_id=36&doc_id=13...

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