30 Jan '17, 8pm

SERDES Design & Verification Challenges

SERDES (SERializer/DESerializer) are high-speed, high-performance mixed-signal IP blocks, which present many challenges to design and verification. The core of both the serializer and deserializer is a high performance PLL, with jitter specs on the order of femtoseconds and lock transients on the order of microseconds. The serial data has bit rates above 10Gb/s and pattern frequencies that stretch below the KHz range. Circuit simulation is a significant challenge at advanced nodes, such as 28nm and below, where full RC simulation is required at many levels, greatly increasing verification time. The Analog FastSPICE (AFS) Platform is the only circuit simulator that could handle the high speed portions of the design with the required SPICE accuracy, while AFS RF is used to ensure the PLLs meet the required phase noise.

Full article: http://spectrum.ieee.org/webinar/serdes-design-and-verifi...

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