11 Nov '17, 9pm

FPGA LVDS I/O as an Analog Programmable Comparator | EE Times

FPGA LVDS I/O as an Analog Programmable Comparator | EE Times

Seeing the new ADC IP being bandied about by FPGA vendors got William Murray wondering what is behind all this. Seeing the new analog-to-digital converter (ADC) IP being bandied around by the FPGA vendors got me wondering what is behind all this. It all boils down to the fact that a comparator is, in essence, a one-bit ADC, while an LVDS I/O receiver is a comparator. Most new FPGA families have LVDS I/O as an option, and it is not hard to add a discrete LVDS RX chip to a CPLD input bank. Thus, a programmable comparator may be created by feeding an LVDS I/O an analog voltage. This may be a single-ended comparator. If two I/Os are employed, a window comparator may be realized. The analog voltage may be created via a pulse-width modulated (PWM) channel within the FPGA, allowing it to self-tune the comparator. This means any unused LVDS channels can be employed for things like...

Full article: https://www.eetimes.com/author.asp?doc_id=1320289&section...

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A reason for getting the MAXimator can be playi...

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IBM's Quantum Computer Goes Commercial | EE Times

eetimes.com 13 Nov '17, 8am

IBM will also provide an open-source quantum information software kit (QIS-Kit ). The key to its QIS-Kit is you don't need...

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