30 Dec '11, 5pm

Our training course on "Advanced #FPGA Implementation" is now updated to ISE Design Suite 13.3. Details:

Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints. Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation. Lab 3: Advanced I/O Timing – Compose timing constraints for source-synchronous and system-synchronous I/O interfaces. Analyze the timing and determine changes to optimize the interface timing. Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool. Lab 5: Floorplanning – Implement a design by using floorplanned constraints to improve the timing results over a design without floorplanning. Lab 6: FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.

Full article: http://www.xilinx.com/training/fpga/advanced-fpga-impleme...

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