30 Jul '14, 9pm

"Ushering in Big-Data & Giga-Scale Design Challenges - EE Times" #BigData #NoSQL

"Ushering in Big-Data & Giga-Scale Design Challenges - EE Times" #BigData #NoSQL

Welcome to the era of "big data." We in EDA (electronic design automation) are starting to experience this trend, as Gary Smith suggested at this year's DAC, which we interpret to mean giga-scale design challenges. Mostly, these are due to increased design size and complexity, coupled with process variation-induced design and fabrication uncertainties with small device geometries at advanced nodes. Giga-scale design challenges come in various forms. For example, designs are becoming larger -- it's not uncommon today to see multibillion transistor SoCs. The transistor count of logic processing chips increases by about 2x every two years, and the instance of on-die embedded SRAM is increasing rapidly. With more complex designs, advanced SoCs are integrating different types of IP for more functionality. Multimode, multisupply operations place additional challenges on SoC desi...

Full article: http://www.eetimes.com/author.asp?section_id=36&doc_id=13...

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