30 Mar '12, 9pm

DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups #CDNS #EDA

On the last day of February 2012, I presented a proposal at the DVCon 2012 Conference to extend SystemVerilog to support a real data type in coverpoint objects in order to facilitate mixed-signal verification for functional coverage. The paper, titled “Bringing Continuous Domain into SystemVerilog Covergroups, ” reflected a year-long effort between Cadence R&D and Scott Little of Freescale (Scott moved to Intel just before we submitted our work to DVCon) that culminated in a prototype of SystemVerilog real coverage in action. We wanted to share this development with the digital verification community that usually represents the majority of DVCon crowd. After providing a brief refresher on functional coverage basics, the paper went on to ask: “How do analog effects get captured in functional coverage while performing system level verification?” Since analog effects are desc...

Full article: http://www.cadence.com/Community/blogs/ms/archive/2012/03...

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