27 Apr '12, 5am

Rick Merritt's piece in EETimes on latest move to commercialize a 3D (multi-chip module) semiconductor device at 20nm.

Rick Merritt's piece in EETimes on latest move to commercialize a 3D (multi-chip module) semiconductor device at 20nm.

MOUNTAIN VIEW, Calif. – Next-generation 20 nm processes can support optimized versions for low power and high performance, according to an IBM expert. GlobalFoundries will decide in August whether or not it will offer such variations. Those were just two data points from wide ranging discussions at the GSA Silicon Summit here. Separately, executives said a variety of 3-D ICs will hit the market in 2014 despite numerous challenges, and CMOS scaling is slowing down but still viable through a 7 nm node. “Recently TSMC said at 20 nm there are no significant differences [in process optimizations], but I don’t believe that,” said Subramanian Iyer, an IBM fellow and chief technologist in its microelectronics division. “I believe at same node you can have two [different variations],” he said in a keynote here. Indeed, GlobalFoundries is debating whether it wants to offer high perf...

Full article: http://www.eetimes.com/electronics-news/4371833/Chip-exec...

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