27 Apr '12, 3pm

A modeling approach for power integrity simulation in 3D-IC designs: via @ee_times #EDA #SemiEDA

A modeling approach for power integrity simulation in 3D-IC designs: via @ee_times #EDA #SemiEDA

Designing reliable three-dimensional (3D) system-on-chips (SoCs) is extremely complex, and critical for the next level of integration in silicon design. In 3D integrated circuit (3D-IC) vertical stacked-die architecture, individual die are connected directly by Through-Silicon-Vias (TSVs) and micro-bumps. Simulation of 3D-ICs for power integrity needs to model the 3D structure, including all the ICs and their TSV interconnects. Some challenges include modeling and integrating third-party application SoCs or memories into the current design framework and performing a complete analysis. This article outlines an approach for concurrent analysis of the 3D-IC power grid, as well as a chip model-based analysis, and how analysis based on a chip macro-model can yield the same results as concurrent full-chip analysis, resulting in significant runtime benefits. Un derstanding multi-...

Full article: http://www.eetimes.com/design/eda-design/4371855/A-modeli...

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The voltage-amplifier stage (or VAS) has often been regarded as the most critical part of a power-amplifier, since it not ...