30 Dec '14, 8pm

SoC clock monitoring issues: Scenarios and root cause analysis

SoC clock monitoring issues: Scenarios and root cause analysis

The Clock Monitoring Unit monitors the Fast Oscillator Clock as well as PLLs with Internal RC Oscillator Clock as the reference. The frequency of Fast Oscillator is compared against the minimum value configured by the user in the Monitoring Unit. In case the EXTAL frequency goes below the specified limit or is cut off completely due to damage of the external crystal, a fault signal is generated by the clock monitoring unit which then goes to the Reset generation module of the SOC. The Reset generation module is software configurable for the reaction in case of a loss of oscillator clock situation. It can be configured for a long/short reset, interrupt or safe mode entry through Mode control module of the SOC (Safe mode is the chip mode in which all the clocks are switched off and the entire system gracefully moves to Internal Oscillator as the system clock).

Full article: http://www.edn.com/design/integrated-circuit-design/44380...

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