31 May '12, 3pm

Cadence tools out 20nm SoC test chip for STMicro - EE Times: #tools

MANHASSET, NY -- Cadence Design Systems has announced it has helped tape out STMicroelectronics’ 20nm test SoC chip, an industry milestone for Cadence delivering an end-to-end mixed-signal design flow for 20 nm. "Working together over the past two years, Cadence and STMicroelectronics successfully deployed an efficient methodology and design automation to address the requirements for designing complex mixed-signal SoCs," said Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence, in a statement. ST performed automated layout generation using Cadence Virtuoso Layout Suite into STMicroelectronics' custom IP design development, including foundation IP, PLL and video DAC. Designers used a 20nm design kit that enables advanced capability such as Modgens, constraints and space-based routing. The Encounter Digital Implementation (EDI)...

Full article: http://www.eetimes.com/electronics-news/4374161/Cadence-t...

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