19 Oct '15, 8am

Mentor massively accelerates verification: Mentor massively accelerates verification Ever-increas... #electronics

Mentor massively accelerates verification: Mentor massively accelerates verification Ever-increas... #electronics

"Networking chips are now the biggest chips out there - they can be bigger than 20x20mm and have more than 400 million gates," says Brunet. "Simulation is insufficient because of the limit to cycles per second. Emulation accelerates the verification process by one million times over simulation." "The current approach is not scalable, " adds Brunet, "we need a scalable solution to one billion gates - there's a need for lab virtualisation." Which is why Mentor has launched the Veloce VirtuaLab Ethernet environment, with support for 25G, 50G and 100G Ethernet. This support enables efficient, emulation-based verification for the massive Ethernet-based designs being created today. The huge surge in demand for connectivity has had a profound effect on the size of switch and router designs, making them among the largest IC designs developed today. The sheer size of the designs, t...

Full article: http://www.electronicsweekly.com/news/circuits/mentor-mas...

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