26 Nov '15, 4pm

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It is a 12-bit resolution analogue-to-digital converter (ADC) which has a sampling rate of 5.4Gsample/s, an instantaneous bandwidth in excess of 3GHz and latency as low as 26 clock cycles with a noise of -150dBm/Hz. According to the supplier, it will be “be free of non-harmonic spurs”. The device has a simultaneous sampling mode which averages its four ADC cores to gain 6dB of signal to noise ratio. Designated the EV12AS350, the ADC is defence systems and test and measurement applications. “This is an ADC with no non-harmonic spurs, which will allow coders to achieve previously unimagined performance in their systems,” said Richard Gibbs, president of e2v Semiconductors. According to Laurent Monge, v-p and general manager of e2v Semiconductors, the enhanced version of the EV12AS350 ADC will be available for general sampling next year.

Full article: http://www.electronicsweekly.com/news/e2v-super-adc-is-fr...

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