29 Apr '16, 11pm

Control an #FPGA bus without using the processor:

Many FPGA designs use an embedded processor for control. A typical solution involves the use of a soft processor such as a Nios, though FPGA SoCs with a built-in hard processor have become popular too. Figure 1 shows a typical Altera FPGA system that contains the processor and a mix of peripherals that are connected via Altera’s Avalon Memory Mapped (MM) bus. These processors greatly simplify the end application, but require a strong programing background and knowledge of complicated toolchains. This can hinder debug, especially if a hardware engineer needs a simple way to read and write to the peripherals without pestering the software engineer.

Full article: http://www.edn.com/design/integrated-circuit-design/44419...

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