Verification has become the biggest challenge in SoC development. However, traditional verification tools haven’t kept pace with how quickly SoC and ASIC design size and complexity are growing. Simulators slow to a grind as RTL and gate design size increase. This, in turn, delays system integration and extends the overall verification cycle. As the industry's first datacenter-class emulation system, the Palladium® Z1 platform bridges the verification productivity gap to accelerate verification of SoCs, subsystems, and IP blocks, as well as system-level validation. Compared to the previous generation, the platform, which brings together simulation acceleration and emulation technologies, delivers up to 5X better emulation throughput and, on average, 2.5X better workload efficiency than the closest competitor.